Multi-core microcontroller systems are often implemented in such a manner that all available cores can access the same resources, for example memory or peripherals. A “memory management unit” (MMU) or “memory protection unit” (MPU) or “system memory protection unit” (SMPU) is usually provided for the purpose of controlling access to specific memory areas or peripherals and can be used to control memory access for applications executed on the cores. For reasons of safety, only a main core provided for this purpose has write rights for registers of the memory management unit in order to configure the access authorization of the secondary cores. Such a restriction of the access authorization for the secondary cores can be achieved, in particular, by means of appropriate implementation in hardware. For example, basic software and safety-relevant software are executed by the main core and application-specific software is accordingly executed by the secondary cores.
For example, information relating to blocked write access operations of a secondary core to memory areas which have not been enabled for write access operations for this secondary core can be stored until the corresponding flags in error registers of the memory management unit have been deleted. Unlike the main core, the secondary cores cannot delete these flags, with the result that the access operations following a first blocked access operation cannot be captured and useful information may therefore possibly be lost if the system state is logged, for example in the event of a blocked write access operation. It is often not possible to authorize a fundamental write authorization of the secondary cores for these error registers for reasons of maintaining a safety requirement level of the functional safety of the underlying system.